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1 ltc1479 powerpath controller for dual battery systems features descriptio n u n complete power path management for two batteries, dc power source, charger and backup n compatible with li-ion, nicd, nimh and lead-acid battery chemistries n 3-diode mode ensures powers is available under cold start conditions n all n-channel switching reduces power losses n capacitor and battery inrush current limited n seamless switching between power sources n independent charging and monitoring of two battery packs n new, small footprint, 36-lead ssop package the ltc ? 1479 is the heart of a total power management solution for single and dual battery notebook computers and other portable equipment. the ltc1479 directs power from up to two battery packs and a dc power source to the input of the main system switching regulator. it works in concert with related ltc power management products (e.g. ltc1435, lt ? 1511, etc.) to create a total system solution; starting from the batteries and the dc power source, and ending at the input of each of the computers complex loads. a system-provided power management m p monitors and actively directs the ltc1479. the ltc1479 uses low loss n-channel mosfet switches to direct power from three main sources. an adaptive current limiting scheme reduces capacitor and battery inrush current by controlling the gates of the mosfet switches during transitions. the ltc1479 interfaces di- rectly to the lt1510, lt1511 and lt1620/ltc1435 bat- tery charging circuits. typical applicatio n u dual battery powerpath tm controller system block diagram powerpath is a trademark of linear technology corporation. , ltc and lt are registered trademarks of linear technology corporation. n notebook computer power management n portable instruments n handheld terminals n portable medical equipment n portable industrial control equipment applicatio n s u bat1 bat2 battery charger (lt1510/lt1511/ lt1620/ltc1435) sw a/b r sense sw c/d sw e/f sw g sw h + c in dcin 1479 ta01 5v ac adapter power management p backup regulator (lt1304) high efficiency dc/dc switching regulator (ltc1435/ltc1438 etc.) ltc1479 powerpath controller status & control
2 ltc1479 absolute m axi m u m ratings w ww u package/order i n for m atio n w u u order part number t jmax = 100 c, q ja = 95 c/ w consult factory for military grade parts. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 top view g package (209 mils) 36-lead plastic ssop 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 dcin dcdiv lobat ga sab gb gc scd gd ge sef gf sense + sense v cc v gg v + sw v bkup bat1 bat2 bdiv v bat chgmon batsel gg sg gh sh dcingood dcin/bat batdis 3dm chgsel v ccp gnd dcin, bat1, bat2 supply voltages .......... C 0.3v to 32v sense + , sense C , v bat , v + ..................... C 0.3v to 32v ga, gb, gc, gd, ge, gf, gg, gh .............. C 0.3v to 42v sab, scd, sef, sg, sh ............................ C 0.3v to 32v sw, v gg ................................................... C 0.3v to 42v dcdiv, bdiv ............................................ C 0.3v to 5.5v all logic inputs (note 1).......................... C 0.3v to 7.5v all logic outputs (note 1) ....................... C 0.3v to 7.5v v cc regulator output current ................................ 1ma v ccp regulator output current .............................. 1ma v + output current .................................................. 1ma v gg regulator output current ............................ 100 m a operating temperature ltc1479cg ............................................. 0 c to 70 c LTC1479IG ........................................ C 40 c to 85 c junction temperature........................................... 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c symbol parameter conditions min typ max units power supplies v dcin dcin operating range (mode 1) dcin selected 6 28 v v bat1 battery 1 operating range (mode 5) battery 1 selected 6 28 v v bat2 battery 2 operating range (mode 6) battery 2 selected 6 28 v v bkup backup operating range (mode 8) backup operation 6 28 v i dcin dcin operating current (mode 1) dcin selected 175 500 m a i vbat1 battery 1 operating current (mode 5) battery 1 selected 150 500 m a i vbat2 battery 2 operating current (mode 6) battery 2 selected 150 500 m a i vbkup backup operating current (mode 8) backup operation (v bkup = 6v) 40 100 m a v ccp v ccp regulator output voltage (modes 1, 5, 6) dcin, battery 1 or battery 2 selected l 4.0 4.8 6.0 v v cc v cc regulator output voltage (modes 1, 5, 6) dcin, battery 1 or battery 2 selected l 3.3 3.6 3.9 v v gg v gg gate supply voltage (modes 1, 5, 6) dcin, battery 1 or battery 2 selected l 34.0 36.3 40.0 v v uvlo uv lockout threshold (mode 9) no power, v batx falling from 12v 4.0 4.5 5.0 v v uvlohys uv lockout hysteresis (mode 9) no power, v batx rising from 1v 0.2 0.5 1.0 v v dcin = 25v, v bat1 = 16v, v bat2 = 12v, t a = 25 c unless otherwise noted. (note 2) dc electrical characteristics ltc1479cg LTC1479IG
3 ltc1479 v dcin = 25v, v bat1 = 16v, v bat2 = 12v, t a = 25 c unless otherwise noted. (note 2) dc electrical characteristics symbol parameter conditions min typ max units dcin good monitor v thdcdiv dcdiv threshold voltage (mode 1) v dcdiv rising from 1v to 1.5v l 1.190 1.215 1.240 v v hysdcdiv dcdiv hysteresis voltage (mode 1) v dcdiv falling from 1.5v to 1v 10 35 50 mv i biasdcdiv dcdiv input bias current (mode 1) v dcdiv = 1.5v 20 na v lodcgd dcingood output low voltage (mode 1) v dcdiv = 1v, i dcingood = 100 m a 0 0.1 0.4 v i pudcgd dcingood pull-up current (mode 1) v dcdiv = 1.5v, v dcingood = 0v 1 2 6 m a i lkgdcgd dcingood leakage current (mode 1) v dcdiv = 1.5v, v dcingood = 7v 1 m a battery monitor v thlobat low-battery threshold voltage (modes 5, 6) v bdiv falling from 1.5v to 1v l 1.190 1.215 1.240 v v hyslobat low-battery hysteresis voltage (modes 5, 6) v bdiv rising from 1v to 1.5v 10 35 50 mv i biasbdiv bdiv input bias current (modes 5, 6) v bdiv = 1.5v 20 na v lolobat lobat output low voltage (modes 5, 6) v bdiv = 1v, i lobat = 100 m a 0 0.1 0.4 v i lkglobat lobat output leakage current (modes 5, 6) v bdiv = 1.5v, v lobat = 7v 1 m a r onbatsw battery switch on resistance (modes 5, 6) each switch tested independently 200 400 800 w i lkgbatsw battery switch off leakage (modes 5, 6) each switch tested independently 1 m a gate drivers v gs(on) gate-to-source on voltage (ga to gf) (modes 1, 2, 4, 5, 6) i gs = C1 m a 5.0 5.5 7.0 v gate-to-source on voltage (gg, gh) (modes 2, 4) i gs = C1 m a 4.5 5.2 7.0 v v gs(off) gate-to-source off voltage (modes 1, 2, 4, 5, 6) i gs = 100 m a 0 0.4 v i bsense + sense + input bias current (modes 1, 5, 6) 5 15 30 m a i bsense C sense C input bias current (modes 1, 5, 6) 5 15 30 m a v sense inrush current limit sense voltage (modes 1, 5, 6) l 0.15 0.20 0.25 v i pdsab sab pull-down current (modes 5, 6) v sab = 10v 30 100 300 m a i pdscd scd pull-down current (mode 1) v scd = 10v 30 100 300 m a i pdsef sef pull-down current (mode 1) v sef = 10v 30 100 300 m a i pdsg sg pull-down current (mode 1) v sg = 10v 3 ma i pdsh sh pull-down current (mode 1) v sh = 10v 3 ma charge monitor r oncmon chgmon switch on resistance (modes 5, 6) each switch tested independently 50 150 250 w i lkgcmon chgmon switch off leakage (modes 5, 6) each switch tested independently 1 m a digital inputs v hidigin input high voltage (mode 1) all digital inputs l 2v v lodigin input low voltage (mode 1) all digital inputs l 0.8 v i hidigin input leakage current (mode 1) all digital inputs, v diginx = 7v 1 m a i lodigin input leakage current (mode 1) v diginx = 0v (note 3) 1 m a i pudigin input pull-up current (mode 1) v diginx = 0v (note 4) 1 2 6 m a
4 ltc1479 ac electrical characteristics v dcin = 25v, v bat1 = 16v, v bat2 = 12v, t a = 25 c unless otherwise noted. (note 2) symbol parameter conditions min typ max units t onga/gb gate a/b turn-on time v gs > 3v (note 5) 30 m s t ongc/gd gate c/d turn-on time v gs > 3v (note 5) 30 m s t onge/gf gate e/f turn-on time v gs > 3v (note 5) 30 m s t offga/gb gate a/b turn-off time v gs < 1v (note 5) 3 m s t offgc/gd gate c/d turn-off time v gs < 1v (note 5) 3 m s t offge/gf gate e/f turn-off time v gs < 1v (note 5) 3 m s t ongg/gh gate g/h turn-on time v gs > 3v (note 5) 300 m s t offgg/gh gate g/h turn-off time v gs < 1v (note 5) 5 m s f ovgg v gg reg operating frequency 30 khz t dlobat lobat delay times d v bdiv = 100mv, r pullup = 51k 5 m s t ddcingood dcingood delay times d v dcdiv = 100mv, r pullup = 51k 5 m s the l denotes specifications which apply over the full operating temperature range. note 1: the logic inputs are high impedance cmos gates with esd protection diodes to ground and therefore should not be forced below ground. these inputs can however be driven above the v ccp or v cc supply rails as there are no clamping diodes connected between the input pins and the supply rails. this facilitates operation in mixed 5v/3v systems. note 2: the selected operating mode truth table, which defines the operating conditions and logical states associated with each normal operating mode, should be used in conjunction with the electrical characteristics table to establish test conditions. actual production test conditions may be more stringent. note 3: the following inputs are high impedance cmos inputs: 3dm and dcin/bat and have no internal pull-up current. note 4: the following inputs have built-in 2 m a pull-up current sources (passed through series diodes): batsel, batdis and chgsel. note 5: gate turn-on and turn-off times are measured with no inrush current limiting, i. e., v sense = 0v, using si4936dy mosfets in the typical application circuit. truth table selected modes logic inputs switch status outputs sw sw sw sw sw no. mode 3dm dcin/bat batsel batdis chgsel a/b c/d e/f g h chgmon v bat lobat dcingood 1 dc operation h h h l h on off off off off hi-z bat1 h h 2 dc operation and h h h h h on off off on off bat1 bat1 h h bat1 charging 3 dc operation and h h l l l on off off off off hi-z bat2 h h bat2 disconnected 4 dc operation and h h l h l on off off off on bat2 bat2 h h bat2 charging 5 bat1 operation h l h h h off on off off off hi-z bat1 h l 6 bat2 operation h l l h h off off on off off hi-z bat2 h l 7 bat1 low and h l h l h off off off off off hi-z bat1 l l disconnected 8 backup operation h l h l h off off off off off hi-z bat1 l l 9 no power l l l l l off off off off off hi-z bat2 l l (no backup) 10 dc reconnected l l h l h 3dm* 3dm* 3dm* off off hi-z bat1 l h 11 dc connected h h h l h on off off off off hi-z bat1 l h and reset (selected operating modes) * 3dm = three diode mode. when this mode is invoked, only the first mosfet switch in each back-to-back switch pair, i. e., sw a, sw c and sw e is turned on. current may still pass through the inherent body diode of the idled switches, i.e., sw b, sw d and sw f to help restart the system after abnormal operating conditions have been encountered. see the timing diagram and applications information sections for further details.
5 ltc1479 typical perfor m a n ce characteristics u w dcin supply current bat1 supply current bat2 supply current v gg supply voltage junction temperature ( c) ?0 38 40 44 25 75 1479 g05 36 34 ?5 0 50 100 125 32 30 42 v gg supply voltage (v) mode 1 v dcin = 24v v bkup supply current v bkup supply voltage (v) 0 40 50 70 15 25 1479 g04 30 20 510 20 30 35 10 0 60 v bkup supply current ( m a) mode 8 no other power t j = 25 c v cc supply voltage junction temperature ( c) ?0 3.7 3.8 4.0 25 75 1479 g06 3.6 3.5 ?5 0 50 100 125 3.4 3.3 3.9 v cc supply voltage (v) mode 1 v dcin = 24v v ccp supply voltage junction temperature ( c) ?0 5.0 5.5 6.5 25 75 1479 g07 4.5 4.0 ?5 0 50 100 125 3.5 3.0 6.0 v ccp supply voltage (v) mode 1 v dcin = 24v dcin supply voltage (v) 0 200 250 350 15 25 1479 g01 150 100 510 20 30 35 50 0 300 dcin supply current ( m a) mode 1, dcdiv = 1.5v no other power t j = 25 c bat1 supply voltage (v) 0 200 250 350 15 25 1479 g02 150 100 510 20 30 35 50 0 300 bat1 supply current ( m a) mode 5 no other power t j = 25 c bat2 supply voltage (v) 0 200 250 350 15 25 1479 g03 150 100 510 20 30 35 50 0 300 bat2 supply current ( m a) mode 6 no other power t j = 25 c
6 ltc1479 pi n fu n ctio n s uuu external power supply pins dcin (pin 1): supply input. a 330 w resistor should be put in series with this pin and the external dc power source. a 0.1 m f bypass capacitor should be connected to this pin as close as possible. dcdiv (pin 2): supply divider input. this is a high impedance comparator input with a 1.215v threshold (rising edge) and approximately C 35mv hysteresis. bat1, bat2 (pins 35, 34): supply input. these two pins are the inputs from the two batteries. a 1 m f bypass capacitor should be connected to each pin as close as possible if there is no larger battery supply capacitor within 2". v bat (pin 32): battery voltage sense. this pin connects the top of the battery resistor ladder to either bat1 or bat2. bdiv (pin 33): battery divider input. a high impedance comparator input with a 1.215v threshold (falling edge) and approximately 35mv hysteresis. v bkup (pin 36): supply input. this input supplies power to the ltc1479 when in the backup mode of operation. a 1 m f bypass capacitor should be connected to the v bkup pin as close as possible if there is no larger backup supply capacitor within 2". internal power supply pins v ccp (pin 20): power supply output. bypass this output with at least a 0.1 m f capacitor. the v ccp power supply is used primarily to power internal logic circuitry. v cc (pin 15): power supply output. this is a nominal 3.60v output. bypass this regulator output with a 2.2 m f tantalum capacitor. this capacitor is required for stability. v + (pin 17): supply. the v + pin is connected via three internal diodes to the dcin, bat1 and bat2 pins and powers the top of the v gg switching regulator inductor. bypass this pin with a 1 m f/35v capacitor. v gg (pin 16): gate supply. this high voltage (36.5v) switching regulator is intended only for driving the internal micropower gate drive circuitry. do not load this pin with any external circuitry. bypass this pin with a 1 m f/50v capacitor. sw (pin 18): output. this pin drives the bottom of the v gg switching regulator inductor which is connected between this pin and the v + pin. gnd (pin 19): ground. the v gg and v + bypass capacitors should be returned to this ground which is connected directly to the source of the n-channel switch in the v gg regulator. input power switches ga, gb (pins 4, 6): dcin switch gate drive. these two pins drive the gates of the back-to-back n-channel switches in series with the dcin input. sab (pin 5): source return. the sab pin is connected to the sources of sw a and sw b. a small pull-down current source returns this node to 0v when the switches are turned off. gc, gd (pins 7, 9): bat1 switch gate drive. these two pins drive the gates of the back-to-back n-channel switches in series with the bat1 input. scd (pin 8): source return. the scd pin is connected to the sources of sw c and sw d. a small pull-down current source returns this node to 0v when the switches are turned off. ge, gf (pins 10, 12): bat2 switch gate drive. these two pins drive the gates of the back-to-back n-channel switches in series with the bat2 input. sef (pin 11): source return. the sef pin is connected to the sources of sw e and sw f. a small pull-down current source returns this node to 0v potential when the switches are turned off. sense + (pin 13): inrush current input. this pin should be connected directly to the top (switch side) of the low valued resistor in series with the three input power selector switch pairs, sw a/b, sw c/d and sw e/f, for detecting and controlling the inrush current into and out of the power supply sources and the output capacitor.
7 ltc1479 pi n fu n ctio n s uuu sense C (pin 14): inrush current input. this pin should be connected directly to the bottom (output side) of the low valued resistor in series with the three input power selector switch pairs, sw a/b, sw c/d and sw e/f, for detecting and controlling the inrush current into and out of the power supply sources and the output capacitor. battery charging switches gg, gh (pins 29, 27): charger switch gate drive. these two pins drive the gates of the back-to-back n-channel switch pairs, sw g and sw h, between the charger output and the two batteries. sg, sh (pin 28, 26): source returns. these two pins are connected to the sources of sw g and sw h respectively. a small pull-down current source returns these nodes to 0v when the switches are turned off. chgmon (pin 31): battery selector output. this pin is the output of an internal switch which is connected to bat1 and bat2 and connects the positive terminal of the selected battery to the voltage feedback resistors in the charger circuit. microprocessor interface dcingood (pin 25): comparator output. this open-drain output has an internal 2 m a pull-up current source con- nected through a diode to the v ccp power supply. an external pull-up resistor can be added if more pull-up current is required. this output is active high when the dc supply rises above the programmed voltage. lobat (pin 3): comparator output. this open-drain out- put does not have an internal pull-up current source and is active low when the selected battery voltage drops below the programmed voltage. dcin/bat (pin 24): selector input. this high impedance logic input allows the m p to make the ultimate decision on the connection of the dc power source, based upon the dcingood pin information. in some minimized systems, the dcin/bat pin may be connected directly to the dcingood pin. batdis (pin 23): battery disconnect input. this high- impedance logic input has a built-in 2 m a pull-up current source and allows the m p to disconnect the battery from the system. 3dm (pin 22): three diode mode input. this high imped- ance logic input has no built-in pull-up current source. connect a 100k resistor from this pin to ground to ensure three diode mode operation from a cold start. chgsel (pin 21): battery charger selector input. this high impedance logic input has a built-in 2 m a pull-up current source and allows the m p to determine which battery is being charged by connecting the selected battery to the charger output via one of the switch pairs, sw g or sw h. (the charger voltage feedback ladder is simultaneously switched to the selected battery.) batsel (pin 30): battery selector input. this high imped- ance logic input has a built-in 2 m a pull-up current source and allows the m p to select which battery is connected to the system and the battery monitor comparator input. battery 1 is selected with a logic high on this input and battery 2 is selected with a logic low.
8 ltc1479 block diagra m w dcdiv ga gb sab v sense + v sense bat2 inrush sense bat1 inrush sense dcin inrush sense gc gd scd ge gf sef bat1 bat2 dcin v + sw v cc v gg bat1 bat2 dcin bdiv bat2 bat1 v bat chgmon batsel chgsel sw g gate driver sg gg sw h gate driver sh gh v ccp dcingood lobat gnd dcin 3dm dcin/bat 2 m a v ccp batdis 2 m a v ccp v ccp 2 m a v ccp 2 m a v ccp 1479 bd dcin monitor sw a/b gate drivers sw c/d gate drivers sw e/f gate drivers v cc regulator & bias generator v gg switching regulator battery monitor switch control logic v bkup
9 ltc1479 ti i g diagra s w w u dc and battery operation timing dcin dcingood dcin/bat batsel mode 1 dc operation bat1 disconnected mode 2 dc operation bat1 charging chgsel mode 3 dc operation bat2 disconnected mode 4 dc operation bat2 charging batdis mode 5 bat1 operation mode 6 bat2 operation note: for modes 1 to 6, 3dm = h, bat1 = 16v, bat2 = 12v 25v 25v (16v) (12v) 1479 td01 0v output 0v backup and dc restoration timing dcin mode 7 bat1 low & disconnected mode 8 backup operation mode 9 no power (no backup) mode 10 dc restored (three diode mode) batdis mode 11 dc reconnected (sw a/b on) mode 12 three diode mode note: for modes 7 to 12, batsel = h, bat1 = 16v and discharging, bat2 = 0v 25v 25v 0v output 0v dcin/bat 3dm lobat bat1 discharging (v bkup = 6v) (0v) (24.3v) (24.3v) 1479 td02 (25v)
10 ltc1479 operatio n u the ltc1479 is responsible for low-loss switching at the front end of the power management system, where up to two battery packs and a dc power source can be indiscriminately connected and disconnected. smooth switching between input power sources is accomplished with the help of low-loss n-channel switches driven by special gate drive circuitry which limits the inrush current in and out of the battery packs and the system power supply capacitors. all n-channel switching the ltc1479 drives external back-to-back n-channel mosfet switches to direct power from the three main power sources: the external dc power source, the pri- mary battery and the secondary battery connected to the main supply pinsdcin, bat1 and bat2 respectively. (n-channel mosfet switches are more cost effective and provide lower voltage drops than their p-channel counterparts.) gate drive (v gg ) power supply the gate drive for the low-loss n-channel switches is supplied by a micropower boost regulator which is regu- lated at approximately 36.5v. the v gg supply provides sufficient headroom above the maximum 28v operating voltage of the three main power sources to ensure that the mosfet switches are fully enhanced. the power for this inductor based regulator is taken from three internal diodes as shown in figure 1. the three figure 1. v gg switching regulator bat1 bat2 dcin v + sw gnd 1479 f01 v gg + + l1 1mh c1 1 m f 35v c2 1 m f 50v to gate drivers (36.5v) ltc1479 v gg switching regulator diodes are connected to each of the three main power sources, dcin, bat1 and bat2. the highest voltage potential is directed to the top of the boost regulator inductor to maximize regulator efficiency. c1 provides filtering at the top of the 1mh switched inductor, l1, which is housed in a small surface mount package. a fourth internal diode directs the current from the 1mh inductor to the v gg output capacitor, c2, further reducing the external parts count. in fact, as demonstrated in figure 1, only three external components are required by the v gg regulator, l1, c1 and c2. inrush current limiting the ltc1479 uses an adaptive inrush current limiting scheme to reduce current flowing in and out of the three main power sources and the dc/dc converter input ca- pacitor during switch-over transitions. the voltage across a single small-valued resistor, r sense , is measured to ascertain the instantaneous current flowing through the three main switch pairs, sw a/b, sw c/d, and sw e/f during the transitions. figure 2 is a block diagram showing only the dcin switch pair, sw a/b. (the gate drive circuits for switch pairs sw c/d and sw e/f are identical). a bidirectional current sensing and limiting circuit determines when the voltage drop across r sense reaches plus or minus 200mv. the gate-to-source voltage, v gs , of the appropriate switch is limited during the transition period until the inrush current subsides, generally within a few milliseconds, depending upon the value of the dc/dc converter input capacitor. v sense + v sense ga gb sab sw a sw b r sense v gg ltc1479 1479 f02 dcin + output to dc/dc converter c out 6v 6v 200mv threshold sw a/b gate drivers bidirectional inrush current sensing and limiting figure 2. sw a/b inrush current limiting
11 ltc1479 operatio n u this scheme allows capacitors and mosfet switches of differing sizes and current ratings to be used in the same system without circuit modifications. after the transition period has passed, the v gs of both mosfets in the selected switch pair rises to approxi- mately 6v. the gate drive is set at 6v to provide ample overdrive for logic level mosfet switches without ex- ceeding their maximum v gs rating. internal power supplies two internal supplies provide power for the control logic and power source monitoring functions. the v ccp logic supply is approximately 5v and provides power for the majority of the internal logic circuitry. the v cc supply is approximately 3.60v and provides power for the v gg switching regulator control circuitry and the gate drivers. the v cc supply has an undervoltage lockout circuit which minimizes power consumption in the event of a total loss of system power; i.e., when all available power sources fall below approximately 4.5v. dcin voltage monitoring the dcin input is continuously monitored via a two resistor ladder connected between the dcin pin and the dcdiv input. the input threshold is 1.215v (rising edge) with approximately C 35mv hysteresis. the use of a defini- tive voltage threshold ensures that the dc supply is not only connected but healthy before being attached to the dc/dc converter input. battery voltage monitoring the ltc1479 has the ability to independently monitor both battery packs. (because of this, one battery pack may be discharged as the other is being charged.) a low-battery detector signals when the selected battery pack has dropped to the level where a shutdown sequence should be initiated or the other battery pack engaged. battery charging management functions the ltc1479 directly interfaces with lt1510/lt1511 battery charger circuits. two gate drive circuits control the two back-to-back n-channel switch pairs, sw g and sw h, under logic (chgsel) control to connect the output of the charger to the selected battery pack. break- before-make action ensures that current does not pass from one battery pack to the other during switch-over of the charger output. the chgsel input also simulta- neously switches the positive terminal of the selected battery pack to the top of the voltage feedback resistor ladder in the charger system through the chgmon pin. backup supply interface power for the ltc1479 is obtained from the backup supply when power is unavailable from the three main sources of power. interface to companion microprocessor a companion m p must be used in conjunction with the ltc1479 to provide overall control of the power manage- ment system. the ltc1479 communicates with the m p by means of five logic inputs and two logic outputs as described in table 1. table 1. ltc1479 m p interface inputs and outputs i nput action dcin/bat logic high required to connect a good dc supply batdis logic low disconnects the battery from the system batsel selects which battery is connected to the system (logic high selects bat1; logic low selects bat2) chgsel selects which battery is charged and monitored (logic high selects bat1; logic low selects bat2) 3dm forces the main three power path switches into 3-diode mode. see applications information section output action dcingood logic high when a good dc supply is present lobat logic low when selected battery voltage is low
12 ltc1479 applicatio n s i n for m atio n wu u u power path switching concepts power source selection the ltc1479 drives low-loss switches to direct power in the main power path of a dual rechargeable battery system the type found in most notebook computers and other portable equipment. figure 3 is a conceptual block diagram which illustrates the main features of an ltc1479 dual battery power management system, starting with the three main power sources and ending at the system dc/dc regulator. switches sw a/b, sw c/d and sw e/f direct power from either the ac adapter (dcin) or one of the two battery packs (bat1 and bat2) to the input of the dc/dc switch- ing regulator. switches sw g and sw h connect the desired battery pack to the battery charger. each of the five switches is intelligently controlled by the ltc1479 which interfaces directly with a power manage- ment system m p. using tantalum capacitors the inrush and outrush current of the system dc/dc regulator input capacitor is limited by the ltc1479. i.e., the current flowing both in and out of the capacitor during transitions from one input power source to another is limited. in many applications, this inrush current limiting makes it feasible to use lower cost/size tantalum surface mount capacitors in place of more expensive/larger alumi- num electrolytics at the input of the dc/dc converter. note: the capacitor manufacturer should be consulted for specific inrush current specifications and limitations and some experimentation may be required to ensure compli- ance with these limitations under all possible operating conditions. back-to-back switch topology the simple spst switches shown in figure 3 actually consist of two back-to-back n-channel switches. these low-loss, n-channel switch pairs are housed in 8-pin so and ssop packaging and are available from a number of manufacturers. the back-to-back topology eliminates the problems associated with the inherent body diodes in power mosfet switches and allows each switch pair to block current flow in either direction when the two switches are turned off. the back-to-back topology also allows for independent control of each half of the switch pair which facilitates bidirectional inrush current limiting and the so called 3- diode mode described in the following section. the 3-diode mode under normal operating conditions, both halves of each switch pair are turned on and off simultaneously. for example, when the input power source is switched from a good dc input (ac adapter) to a good battery pack, bat1, both gates of switch pair sw a/b are turned off and both gates of switch pair sw c/d are turned on. the back-to- back body diodes in switch pair, sw a/b, block current flow in or out of the dc input connector. figure 3. ltc1479 powerpath conceptual diagram bat1 bat2 sw a/b sw c/d sw e/f sw g sw h + high efficiency dc/dc switching regulator 5v 3.3v 12v c in r sense dcin 1479 f03 power management m p ltc1479 powerpath controller battery charger
13 ltc1479 applicatio n s i n for m atio n wu u u the power management m p interface section for additional information on when to invoke 3-diode mode.) component selection n-channel switches the ltc1479 adaptive inrush limiting circuitry permits the use of a wide range of logic-level n-channel mosfet switches. a number of dual low r ds(on) n-channel switches in 8-lead surface mount packages are available that are well suited for ltc1479 applications. the maximum allowable drain source voltage, v ds(max) , of the three main switch pairs, sw a/b, sw c/d and sw e/f, must be high enough to withstand the maximum dc supply voltage. if the dc supply is in the 20v to 28v range, use 30v mosfet switches. if the dc supply is in the 10v to 18v range, and is well regulated, then use 20v mosfet switches. as a general rule, select the switch with the lowest r ds(on) at the maximum allowable v ds . this will minimize the heat dissipated in the switches while increasing the overall system efficiency. higher switch resistances can be toler- ated in some systems with lower current requirements, but care should be taken to ensure that the power dissi- pated in the switches is never allowed to rise above the manufacturers recommended levels. the maximum allowable drain-source voltage, v ds(max) , of the two charger switch pairs, sw g and sw h, need only figure 4. ltc1479 powerpath switches in 3-diode mode bat1 bat2 sw a sw c sw e + high efficiency dc/dc switching regulator 5v 3.3v 12v c in dcin 1479 f04 sw b sw f sw d r sense power management m p ltc1479 powerpath controller on off on off on off in the 3-diode mode, only the first half of each power path switch pair, i.e., sw a, sw c and sw e, is turned on; and the second half, i.e., sw b, sw d and sw f, is turned off. these three switch pairs now act simply as three diodes connected to the three main input power sources as illustrated in figure 4. the power diode with the highest input voltage passes current through to the input of the dc/dc converter to ensure that the power manage- ment m p is powered at start-up or under abnormal oper- ating conditions. (an undervoltage lockout circuit defeats this mode when the v + pin drops below approximately 4.5v). cold start initial condition the ltc1479 is designed to start in the 3- diode mode when all five logic inputs are low when no power is available (including the backup system). a 100k resistor from the 3dm input to ground ensures that this input is low during a cold start. this will cause the main powerpath switches to pass the highest voltage available to the input of the dc/dc converter. normal operation will then resume after a good power source is identified. recovery from uncertain power conditions the 3-diode mode can also be asserted (by applying an active low to the 3dm input) when abnormal conditions exist in the system, i.e., when all power sources are deemed not good or are depleted, or the management system m p is being reset or not functioning properly. (see
14 ltc1479 be high enough to withstand the maximum battery or charger output voltage. in most cases, this will allow the use of 20v mosfet switches in the charger path, while 30v switches are used in the main power path. inrush current sense resistor, r sense a small valued sense resistor (current shunt) is used by the three main switch pair drivers to measure and limit the inrush current flowing through the conducting switch pair. it should be noted that the inrush limiting circuit is not intended to provide short-circuit protection ; but rather, is designed to limit the large peak currents which flow into or out of the large power supply capacitors and the battery packs during power supply switch-over transitions. the inrush current limit should be set at approximately 2 or 3 the maximum required dc/dc input current. for example, if the maximum current required by the dc/dc converter is 2a, an inrush current limit of 6a is set by selecting a 0.033 w sense resistor, r sense , using the following formula: r sense = (200mv)/i inrush note that the voltage drop across the resistor in this example is only 66mv under normal operating conditions. therefore, the power dissipated in the resistor is extremely small (132mw), and a small 1/4w surface mount resistor can be used in this application. a number of small valued, surface mount resistors are available that have been specifically designed for high efficiency current sensing applications. dc input monitor resistor divider the dcdiv input continuously monitors the dc power supply voltage via a two resistor divider network, r dc1 and r dc2 , as shown in figure 5. the threshold voltage of the dc good comparator is 1.215v when the power supply input voltage is rising. approximately C 35mv of hyster- esis is provided to ensure clean switching of the compara- tor when the dc supply voltage is falling. to minimize errors due to the input bias current of the dc good comparator, set r dc1 = 12.1k so that approximately 100 m a flows through the resistor divider when the desired applicatio n s i n for m atio n wu u u figure 5. dc monitor resistor divider ltc1479 dcin dcdiv dc supply to sw a/b r dc1 12.1k 1% r dc2 1% 1.215v dcingood 1479 f05 + batsel bat1 bat2 lobat ltc1479 1479 f06 1.215v v bat bdiv r b1 121k 1% r b2 1% + switch control logic threshold is reached. r dc2 is then selected according to the following formula: r dc2 = 12.1k ?1 v good 1.215v ) ) battery monitor resistor divider a switch controlled by the batsel input connects one of the two batteries to the v bat pin and therefore to the top of the battery resistor divider as shown in figure 6. the threshold voltage of the low-battery comparator is 1.215v when the battery voltage is falling. approximately +35mv of hysteresis is provided to ensure clean switching of the comparator when the battery voltage rises again. to minimize errors due to the input bias current of the low battery comparator, assume r b1 = 121k so that approxi- mately 10 m a flows through the resistor divider when the threshold is reached. r b2 is selected according to the following formula: figure 6. battery monitor resistor divider
15 ltc1479 applicatio n s i n for m atio n wu u u r b2 = 121k ?1 v lobat 1.215v ) ) v gg regulator inductor and capacitors the v gg regulator provides a power supply voltage signifi- cantly higher than any of the three main power source voltages to allow the control of n-channel mosfet switches. this 36.5v micropower, step-up voltage regula- tor is powered by the highest potential available from the three main power sources for maximum regulator effi- ciency. because the three input supply diodes and regulator output diode are built into the ltc1479, only three external components are required by the v gg regulator: l1, c1 and c2 as shown in figure 7. l1 is a small, low current 1mh surface mount inductor. c1 provides filtering at the top of the 1mh switched inductor and should be 1 m f to filter switching transients. the v gg output capacitor, c2, provides storage and filtering for the v gg output and should be 1 m f and rated for 50v operation. c1 and c2 can be either tantalum or ceramic capacitors. v cc and v ccp regulator capacitors the v ccp logic supply is approximately 5v and provides power for the majority of the internal logic circuitry. bypass this output with a 0.1 m f capacitor. the v cc supply is approximately 3.60v and provides power for the v gg switching regulator control circuitry and the gate drivers. bypass this output with a 2.2 m f tantalum capacitor. this capacitor is required for stability of the v cc regulator output . system level considerations the complete power management system the ltc1479 is the heart of a complete power manage- ment system and is responsible for the main power path and charger switching. a companion power management m p provides overall control of the power management system in concert with the ltc1479 and the auxiliary power management systems. a typical dual li-ion battery power management system is illustrated in figure 8. if good power is available at the dcin input (from the ac adapter), switch pair sw a/b are turned onproviding a low-loss path for current flow to the input of the ltc1538-aux dc/dc converter. switch pairs, sw c/d and sw e/f are turned off to block current from flowing back into the two battery packs from the dc input. in this case, an lt1510 constant-voltage/constant-cur- rent (cc/cv) battery charger circuit is used to alternately charge the two li-ion battery packs. the m p decides which battery is in need of recharging by either querying the smart battery directly or by more indirect means. after the determination is made, either switch pair, sw g or sw h, is turned on to pass charger output current to one of the batteries. simultaneously, the selected battery volt- age is returned to the voltage feedback input of the lt1510 cv/cc battery charger via the chgmon output of the ltc1479. after the first battery has been charged, it is disconnected from the charger circuit and the second battery is connected through the other switch pair and the second battery charged. backup power is provided by the lt1304 circuit which ensures that the dc/dc input voltage does not drop below 6v. backup system interface the ltc1479 is designed to work in concert with related power management products including the lt1304 mi- figure 7. v gg step-up switch regulator bat1 bat2 dcin v + sw gnd *coilcraft 1812ls-105 xkbc (708) 639-6400 or equivalent 1479 f07 v gg + + l1* 1mh c1 1 m f 35v c2 1 m f 50v to gate drivers (36.5v) ltc1479 v gg switching regulator
16 ltc1479 applicatio n s i n for m atio n wu u u dcin dcin bat1 bat2 + + v + sw v gg 1 m f 50v 1 m f 50v 1mh* v cc + r sense 0.033 w sw a sw b sw c sw d sw e sw f ga 330 gb gc gd ge gf sab scd sef sense + sense 2 5 + v ccp 2.2 m f 16v 0.1 m f v bat power management m p bdiv v bkup backup regulator ltc1538-aux triple, high efficiency, switching regulator dcdiv 0.1 f ltc1479 lt1510 li-ion battery charger gg sg gh sh chgmon 3.3v 5v sw g sw h dcin li-ion battery pack #1 li-ion battery pack #2 1479 f08 backup nicd *coilcraft 1812ls-105 xkbc (708) 639-1469 12v aux r b2 r b1 r dc2 r dc1 cropower dc/dc converter. as shown in figure 9, the lt1304 monitors the input supply voltage and activates when it drops below 6v. power for the dcin and battery monitors and the logic supply in the ltc1479 is then obtained from the output of the lt1304 step-up regulator. charger system interface the ltc1479 is designed to work directly with constant- voltage (cv), constant-current (cc) battery chargers such as the lt1510 and lt1511. lt1510 battery charger interface as illustrated in figure 10, the lt1510 cv/cc battery charger, takes power from the dc adapter input through schottky diode d1. the output of the charger is directed to from powerpath controller backup nicd cell to input of dc/dc converter l1* 10 h (bold lines indicate high current paths) 5v cc from dc/dc d1 mbr0530 r4 390k 1% r5 100k 1% sw + fb shdn v in gnd lt1304 c1 0.1 m f c3 0.1 m f i lim r3 22k lbi r2 470k 4 8 7 3 5 1479 f09 c2 0.1 m f 1 6 2 lbo 5v cc from dc/dc d2 bas16lt1 q1 2n7002 rohm dta144e r1 10k figure 9. lt1304 micropower backup converter circuit figure 8. simplified dual li-ion battery power management system
17 ltc1479 applicatio n s i n for m atio n wu u u the charging battery through one of the n-channel switch pairs, sw g or sw h. the charging battery voltage is simultaneously connected through the chgmon switch in the ltc1479 to the top of the charger voltage resistor divider, r4 and r5, for constant voltage charging. (see the lt1510 data sheet for further detail.) lt1511 battery charger interface the lt1511, 3a cc/cv battery charger with input current limiting, is connected in a slightly different manner than the lt1510 as illustrated in figure 11. figure 11. interfacing to the lt1511 constant-voltage/constant-current battery charger with input current limiting 1479 f11 sw h si9926dy sw g si9926dy bat1 4 li-ion battery pack bat2 4 li-ion battery pack + + c bat1 47 m f c bat2 47 m f dc input (from ac adaptor) v cc d1 mbrs340t r1 500 w c2 0.33 m f c1 1 m f prog r prog 4.93k 1% r s4 0.05 w c3 200pf v c sw uv boost comp1 spin bat sense gnd c6 0.47 m f c7 50pf c12 1 m f c5 10 m f d3 mbr0540t l1 20 m h d2 mbrs340t lt1511 c4 10 m f ceramic 0.1 m f 330 + c chg 22 m f tant + (charger output) q1 2n7002 r2 1k current control from power management m p + r6 649k 0.25% r5 6.8k r4 5k r3 500 w r7 115k 0.25% r s3 200 w 1% r s2 200 w 1% r s1 0.033 w ovp clp cln to sw c/d to sw e/f to sw a/b + power management m p bat1 bat2 gg sg gh sh chgmon dcin ltc1479 1479 f10 sw h si9926dy sw g si9926dy bat1 4 li-ion battery pack bat2 4 li-ion battery pack + + c bat1 47 m f c bat2 47 m f dc input (from ac adaptor) v cc d1 mbrs140t r2 300 w c1 1 m f prog r prog 11k 1% r3 1k c2 0.1 m f v c sw boost sense bat gnd c3 0.22 m f 0.1 m f d3 1n4148 l1* 33 m h d2 mbrs140t lt1510 c6 10 m f ceramic + c chg 22 m f tant (charger output) q1 2n7002 r1 100k 1% current control from power management m p + r4 649k 0.25% r5 115k 0.25% ovp *coiltronics ctx33-2 to sw c/d to sw e/f to sw a/b 330 + power management m p bat1 bat2 gg sg gh sh chgmon dcin ltc1479 figure 10. interfacing to the lt1510 constant-voltage/constant-current battery charger
18 ltc1479 applicatio n s i n for m atio n wu u u the lt1511 has a third control loop that regulates the current drawn from the ac adapter. therefore, the dc input to the ltc1479 and the input to the host system through sw a/b, is obtained from the output of the lt1511 adapter sense resistor, r s4 , and not directly from the dc input connector as with the lt1510. this allows simultaneous operation of the host system while charging a battery without overloading the ac adapter. charging current is reduced to keep the adapter current within specified levels. however, as with the lt1510 , the output of the lt1511 is directed to the charging battery through either sw g or sw h, and the charging battery voltage is connected to the top of the voltage resistor divider, r6 and r7, for constant voltage charging. (see the lt1511 data sheet for further detail on battery charging techniques and applications hints.) lt1620/ltc1435 battery charger interface the ltc1479 also interfaces with the lt1620/ltc1435 synchronous high efficiency low dropout battery charger. the circuit shown in figure 12 is a constant-current/ constant-voltage battery charger specifically designed for lithium-ion applications having thermal, output current, or input voltage headroom constraints which preclude the use of other high performance chargers such as the lt1510 or lt1511. this circuit can charge batteries at up to 4a. the precision current sensing of the lt1620 combined with the high efficiency and low dropout characteristics of the ltc1435 provide a battery charger with over 96% efficiency requir- ing only 0.5v input-to-output differential at 3a charging current. charge current programming is achieved by applying a 0 m a to 100 m a current from the lt1620 prog pin to ground, which can be derived from a resistor or dac output controlled by the power management m p. (see the lt1620 data sheet for further details on this circuit.) capacitive loading on the chgmon output in most applications, there is virtually no capacitive load- ing on the chgmon outputjust a simple resistor divider. care should be taken to restrict the amount of capacitance to ground on the chgmon output to less than 100pf. if more capacitance is required, it may become necessary to mask the lobat output when the charge monitor is switched between batteries. (internal resis- tance between the bat1 and bat2 inputs and the charge monitor switch may create a transient voltage drop at the v bat output during transitions which could be falsely interpreted by the m p as a low battery condition.) the power management microprocessor interfacing to the ltc1479 the ltc1479 can be thought as a real world interface to the power management m p. it takes logic level commands directly from the m p, and makes changes at high current and high voltage levels in the power path. further, it provides information directly to the m p on the status of the ac adapter, the batteries and the charging system. the ltc1479 logic inputs are ttl level compatible and therefore interface directly with standard power manage- ment m ps. further, because of the direct interface via the five logic inputs and the two logic outputs, there is virtually no latency (i.e. time delay) between the m p and the ltc1479. in this way, time critical decisions can be made by the m p without the inherent delays associated with bus protocols, etc. these delays are acceptable in certain portions of the power management system, but it is vital that the power path switching control be made through a direct connec- tion to the power management m p. the remainder of the power management system can be easily interfaced to the m p through a serial interface. selecting a power management microprocessor the power management m p provides intelligence for the entire power system, is programmed to accommodate the custom requirements of each individual system and allow performance updates without resorting to costly hard- ware changes. the power management m p must meet the requirements of the total power management system, including the ltc1479 controller, the batteries (and interface), the backup system, the charging system and the host proces- sor. a number of inexpensive processors are available which can easily fulfill these requirements.
19 ltc1479 applicatio n s i n for m atio n wu u u 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 c osc run/ss i th sfb sgnd v osense sense + sense tg boost sw v in intv cc bg pgnd v cc ltc1435 + 1 2 3 45 6 7 8 sense i out gnd nin pin v cc prog avg lt1620 + shdn i prog dc input (from ac adapter) to w a/b 330 + r1 1m 0.1% r2 76.8k 0.1% c1 100pf 0.1 f c2 100pf c3 0.1 m f r5 1.5m r5, 1k c4 0.033 m f c6 0.1 m f c5 0.01 m f c8 0.1 m f c9, 100pf c10 100pf c7 0.33 m f r3 10k 1% c11 56pf c12 0.1 m f d1* cmdsh-3 c13 0.33 m f d2* cmdsh-3 q1 si4412dy q2 si4412dy l1 27 m h c15 22 m f 35v 2 r4 0.025 w c14 4.7 m f c16 22 m f 35v 1479 f12 sw h si9926dy sw g si9926dy bat1 4 li-ion battery pack bat2 4 li-ion battery pack + + c bat1 10 m f c bat2 10 m f + to sw c/d to sw e/f + power management m p bat1 bat2 gg sg gh sh chgmon dcin ltc1479 *central semiconductor co. (516) 435-1110 figure 12. interfacing to an lt1620/ltc1435 high efficiency constant-voltage/constant-current battery charger
20 ltc1479 applicatio n s i n for m atio n wu u u interfacing to the battery pack the ltc1479 is designed to work with virtually any battery pack chemistry or cell count, as long as the battery pack operating voltage range is somewhere between 6v and 28v. this permits great flexibility in system design. the low-battery threshold is adjustable and can be set anywhere between 6v and 28v. conventional battery packs conventional battery packs do not include a smart battery interface between the battery pack and the host system. thus, these battery packs generally have only three terminals to connect the battery and a temperature sensor (thermistor) to the host system. the ntc ther- mistor typically has a nominal resistance of 10k at room temperature and is used to monitor the battery pack temperature. lobat and dcingood blanking/filtering it is good practice to include some delay in accepting low battery and dcin good information during transitional periods, e.g., when switching the charger from one battery to another or when switching from batteries to dc power. this technique will eliminate false triggering at the asso- ciated m p i/o. (remember that the 3-diode mode may be used during periods of uncertainty to eliminate the need for instantaneous dcin and battery status information.) smart battery packs smart battery packs, compliant with the smart battery system specification, have a five-terminal connector. two of the terminals are the minus and plus connections to the battery. a third terminal is connected to the top of a thermistor in nicd and nimh battery packs and to a resistor in li-ion battery packs. a fourth and fifth terminal are connected to the smart management bus (smbus) smbdata and smbclk lines from an integrated circuit inside the battery pack. applications assistance linear technology applications engineers have developed a smart battery charger around the lt1511 charger ic. contact the factory for applications assistance in develop- ing a complete smart battery system with intelligent powerpath control using the ltc1479.
21 ltc1479 typical applicatio n s n u dual nimh battery power management system (using an lt1510, 1a charger) 1479 ta02 dcin bat1 bat2 + + v + sw v gg c3 1 m f 50v l1* 1mh c4 1 m f 50v v cc r sense 0.033 w sw a sw b sw c sw d sw e sw f ga gb gc gd ge gf sab scd sef sense + sense v ccp c2 2.2 m f 16v c1 0.1 m f v bat power management m p bdiv v bkup dcdiv ltc1479 gg sg gh sh nicd cell 1812ls-105 xkbc, coilcraft cd43, sumida ctx33-2, coiltronics * ** *** r b2 909k 1% r dc2 205k 1% 330 w r dc1 12.1k 1% r b1 121k 1% + lobat dcingood to input of dc/dc converter l2** 10 m h 3dm 5v cc from dc/dc v cc d1 mbr0530 batsel gnd batdis dcin/bat chgsel dc input (from ac adaptor) v cc d2 mbrs140t r5 300 w c8 1 m f prog r prog 11k 1% r6 1k c9 0.1 m f v c sw boost sense bat gnd c7 0.22 m f d3 1n4148 l3*** 33 m h d4 mbrs140t lt1510 sw h si9926dy c6 10 m f ceramic c chg 22 m f tant (charger output) si4936dy si4936dy (bold lines indicate high current paths) si4936dy sw g si9926dy q1 2n7002 r2 390k 1% r3 100k 1% + + c bat1 10 m f c bat2 10 m f smbus bat2 12-cell nimh battery pack bat1 12-cell nimh battery pack r4 100k 1% chgmon r th1 r th1 r th1 r th2 + + c5 0.1 m f c11 0.1 m f r1 22k 100k r7 470k 4 8 7 3 5 c10 0.1 m f 1 6 2 5v cc from dc/dc d5 bas16lt1 q2 2n7002 rohm dta144e r cm2 909k 1% r cm1 100k 1% r8 10k (backup) 3 6 7 8 5 4 2 1 sw fb shdn v in gnd i lim lbi lbo lt1304 + c dcin 10 m f 35v alum 0.1 m f
22 ltc1479 dual li-ion battery power management system 1479 ta03 dcin 330 w bat1 bat2 + + v + sw v gg c3 1 m f 50v l1* 1mh c4 1 m f 50v v cc r sense 0.033 w sw a sw b sw c sw d sw e sw f ga gb gc gd ge gf sab scd sef sense + sense v ccp c2 2.2 m f 16v c1 0.1 m f v bat power management m p bdiv v bkup dcdiv ltc1479 gg sg gh sh nicd cell 1812ls-105 xkbc, coilcraft dt1608-223, coilcraft ctx33-2, coiltronics * ** *** r b2 909k 1% r dc2 205k 1% r dc1 12.1k 1% r b1 121k 1% + lobat dcingood to input of dc/dc converter l2** 10 m h 3dm 5v cc from dc/dc v cc d1 mbr0530 batsel gnd batdis dcin/bat chgsel dc input (from ac adaptor) v cc d2 mbrs140t r5 300 w c8 1 m f prog r prog 3.83k 1% r6 1k r7 649k 0.25% r8 115k 0.25% c9 0.1 m f v c sw boost sense ovp bat gnd c7 0.22 m f d3 1n4148 l3*** 33 m h d4 mbrs140t lt1510 sw h si9926dy c6 10 m f ceramic c chg 22 m f tant (charger output) si4936dy si4936dy si4936dy sw g si9926dy q1 2n7002 r2 390k 1% r3 100k 1% + + c bat1 10 m f c bat2 10 m f smbus bat2 4 li-ion smart battery pack bat1 4 li-ion smart battery pack chgmon r bat1 r bat1 r bat2 r bat2 + + c5 0.1 m f c11 0.1 m f r1 22k 100k r7 470k 4 8 7 3 5 c10 0.1 m f 1 6 2 5v cc from dc/dc d5 bas16lt1 q2 2n7002 rohm dta144e r8 10k (backup) 1, 7-10, 16 6 7 14, 15 11 6 5 3 2 sw fb shdn v in gnd i lim lbi lbo lt1304 (bold lines indicate high current paths) + c dcin 10 m f 35v alum 0.1 m f typical applicatio n s n u
23 ltc1479 dual li-ion battery power management system (using an lt1511, 3a charger) typical applicatio n s n u 1479 ta04 dcin bat1 bat2 + + v + sw v gg c3 1 m f 50v l1* 1mh c4 1 m f 50v v cc r sense 0.033 w sw a 330 w sw b sw c sw d sw e sw f ga gb gc gd ge gf sab scd sef sense + sense v ccp c2 2.2 m f 16v c1 0.1 m f v bat power management m p bdiv v bkup dcdiv ltc1479 gg sg gh sh nicd cell 1812ls-105 xkbc, coilcraft dt1608-223, coilcraft ctx20-4, coiltronics * ** *** r b2 1.05m 1% r dc2 205k 1% r dc1 12.1k 1% r b1 121k 1% + lobat dcingood to input of dc/dc converter l2** 10 m h 3dm 5v cc from dc/dc v cc d1 mbr0530 batsel gnd batdis dcin/bat chgsel dc input (from ac adaptor) sw h si9926dy si4936dy si4936dy si4936dy sw g si9926dy r2 390k 1% r3 100k 1% + + c bat1 10 m f c bat2 10 m f smbus bat2 4 li-ion smart battery pack bat1 4 li-ion smart battery pack chgmon r bat1 r bat1 r bat2 r bat2 + c5 0.1 m f c15 0.1 m f r1 22k r11 470k 100k 4 8 7 3 5 c14 0.1 m f 1 6 2 5v cc from dc/dc d5 bas16lt1 q2 2n7002 rohm dta144e r12 10k (backup) sw fb shdn v in gnd i lim lbi lbo lt1304 v cc r5 500 w c9 0.33 m f c8 1 m f prog 10 19 18 11 6 2 18 8 14 12 3 1, 4, 5, 7, 16, 23, 24 9 20 to 22 r prog 4.93k 1% c10 200pf v c sw uv boost comp1 spin bat sense gnd c13 0.47 m f c11 50pf c12 1 m f c7 10 m f d3 mbr0540t l3*** 20 m h d2 mbrs340t lt1511 c6 10 m f ceramic + c chg 22 m f tant + c dcin 10 m f 35v alum + (charger output) q1 2n7002 r6 1k r7 649k 0.25% r9 6.8k r10 5k r4 500 w r s4 0.05 w r8 115k 0.25% r s3 200 w 1% r s2 200 w 1% r s1 0.033 w ovp clp cln d1 mbrs340t (bold lines indicate high current paths) 0.1 m f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
24 ltc1479 1479f lt/tp 0697 7k ? printed in usa ? linear technology corporation 1996 dimensions in inches (millimeters) unless otherwise noted. package descriptio n u g package 36-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) related parts part number description comments lt1304 micropower dc/dc step-up converter 5v at 200ma from 2 cells, i q = 10 m a in shutdown ltc1435 high efficiency synchronous step-down converter fixed frequency, ultrahigh efficiency ltc1438 dual high efficiency synchronous step-down converter fixed frequency, pll lockable, ultrahigh efficiency ltc1473 dual powerpath switch driver protected power management building block lt1510 constant-voltage/constant-current battery charger 1.5a internal switch, precision 0.5% reference lt1511 constant-voltage/constant-current 3a battery charger adapter current limit loop ltc1538-aux dual, synchronous controller with aux regulator 5v standby in shutdown lt1620 battery charger current controller 96% efficiency when used with ltc1435 lt1621 dual battery charger current controller for dual loop applications g36 ssop 1196 0.005 ?0.009 (0.13 ?0.22) 0 ?8 0.022 ?0.037 (0.55 ?0.95) 0.205 ?0.212** (5.20 ?5.38) 0.301 ?0.311 (7.65 ?7.90) 1234 5 6 7 8 9 10 11 12 14 15 16 17 18 13 0.499 ?0.509* (12.67 ?12.93) 25 26 22 21 20 19 23 24 27 28 29 30 31 32 33 34 35 36 0.068 ?0.078 (1.73 ?1.99) 0.002 ?0.008 (0.05 ?0.21) 0.0256 (0.65) bsc 0.010 ?0.015 (0.25 ?0.38) dimensions do not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimensions do not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 l (408) 432-1900 fax: (408) 434-0507 l telex: 499-3977 l www.linear-tech.com

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